(1) Field of the Invention
The present invention relates to cache control apparatuses and cache control methods, and in particular to a cache control apparatus which controls a set-associative cache memory shared by a plurality of processors.
(2) Description of the Related Art
Processor systems each including a plurality of processors are classified into tightly-coupled systems in which the same data is accessed by processors which share memory space and loosely-coupled systems in which data is sent and received between processors via a communication means. The tightly-coupled systems are further classified into a system in which a cache memory is shared by processors and a system in which each of processors includes a cache memory.
FIG. 9 is a block diagram showing a configuration of a multiprocessor system of a tightly-coupled system in which a cache memory is shared by processors. The processor system 200 shown in FIG. 9 includes processors 10 and 11, a memory bus 20, a cache control apparatus 201, a cache memory 50, and a main memory 60.
The processors 10 and 11 access the main memory 60 via the memory bus 20.
The cache control apparatus 201 controls the cache memory 50. This cache control apparatus 201 includes a cache control unit 30, and a cache allocation control unit 240.
The cache control unit 30 controls access from the processors 10 and 11 to the main memory 60 in the following manner. In the case where read access is made to the main memory 60 and a target data to be accessed is present in the cache memory 50 (in the case of a cache hit), the cache control unit 30 accesses the cache memory 50 instead of accessing the main memory 60. Generally, access to the cache memory 50 is faster than access to the main memory 60. Thus, the use of the cache memory 50 reduces the time required for the memory access, and thus increases the performance of the whole system.
In the opposite case where the target data is not present in the cache memory 50 (in the case of a cache miss), the cache control unit 30 reads out the data from the main memory 60 and writes the data into the cache memory 50. This enables the cache control unit 30 to access the cache memory 50 when access to the same data is made next.
In addition, in the case where write access to the main memory 60 is made, the cache control unit 30 writes the data into the main memory 60 and also into the cache memory 50. In this way, the coherency of the data is assured between the cache memory 50 and the main memory 60.
The cache allocation control unit 240 allocates parts of the cache capacity of the cache memory 50 to processing units or tasks. Here, a task is a unit of control for integrally managing a flow of processes such as activation, execution, termination, etc. of a program which functions under control of an operating system. There are various kinds of cache capacity allocation methods. For example, in the case where the cache memory 50 is a set-associative cache memory, the cache memory 50 is segmented into fixed capacity units each called a “way”. The cache allocation control unit 240 allocates ways 51a to 51f to processing units or tasks.
Alternatively, the cache memory 50 may be composed of hardware units each called a “memory macrocell”. The cache control apparatus 201 includes, for each of the units, an address calculator, a buffer circuit, a bus arbitrating circuit, etc. Here, an increase in the number of memory macrocells increases the size of the circuit. An increase in the size of the LSI disables fast transmission. This makes it impossible to expect an increase in frequency. A memory macrocell including a plurality of ways solves this problem because the use of such a memory macrocell enables reduction in the number of memory macrocells. For example, in FIG. 9, a pair of the way 51a and the way 51b is included in a memory macrocell. Likewise, a pair of the way 51c and the way 51d and a pair of the way 51e and the way 51f are included in respectively corresponding ones of memory macrocells.
However, since various kinds of circuits are shared within each memory macrocell, access arbitration is performed resulting in latency in the case where access to one of the ways in a memory macrocell and access to another one of the ways in the memory macrocell are made at the same time. Thus, a memory macrocell including many ways frequently requires latency and thus is disadvantageous in terms of processing speed.
In order to solve this problem, the cache allocation control unit 240 is configured to dynamically change the parts of the cache capacity to be allocated to the respective processors 10 and 11 that share the cache memory 50, according to the priority for the processes performed by the processors 10 and 11. In this way, the conventional cache control apparatus 201 enables the processor which executes a process with a high priority to use a large part of cache capacity (for example, see Patent Reference 1: Japanese Unexamined Patent Publication No. 7-248967).